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Recent content by jason_bill

  1. jason_bill

    AD9643 SPI Write Problem

    Thanks, I assigned SDIO as below: assign sdio = (spi_dir)? 1'bz : mosi_sig; assign miso_sig = (spi_dir)? sdio : 1'b0; when R/W bit equal '1' spi_dir is asserted by spi core.
  2. jason_bill

    AD9643 SPI Write Problem

    Hi, I want to write to the AD9643 Register through SPI interface by FPGA. I have developed spi core. Read operation work correctly becuase when i read value of register it returns the default values as same as is mentioned in the data sheet. But the write operation not work. for example i...
  3. jason_bill

    microblaze uart and vhdl code

    Hi, did you see UG744? That's exactly what you want to do.
  4. jason_bill

    doubt about static timing analysis

    hi,i think "static timing analysis is not efficient for asynchronous designs" refer to asynch clock domain no asynch logic. and means that the analyzer don't account the setup and hold time analysis ,Phase relationship,... in its analysis because clocks are not related. it can just extract the...
  5. jason_bill

    vhdl code for 2d 8x8 dct using distributed arithmetic

    hi, i think you'r thinking as software flow and write your code. you should turn your sight to the hardware flow. divide the dct algorithm to the smallest partition like "floating point add/sub" and "floating point mul" module and then build (not write) your primary dct block.
  6. jason_bill

    FIR Filterfloating point co-efficients not synthesizable

    the above question is about floating point and so think the module must be compatible with ieee745 floating point number format.
  7. jason_bill

    FIR Filterfloating point co-efficients not synthesizable

    if that coefficient is an input of the filter module, i think you just need to convert that to single precision(32 bit) or double precision(64 bit) and then apply it to the input of the coefficient. you can convert the floating point value to the single precision floating point using this site...
  8. jason_bill

    How to simulate in modelsim using scripts

    thanks, I did as below: 1. after completion of core generation, in the core directory a file with .xise extention is created. 2. then i opened this file as a project file in ISE. 3. now in the simulation tab i chose the test bench file (board.vhd) and then double click in the below section...
  9. jason_bill

    How to simulate in modelsim using scripts

    Hi I make a PCI Express core using core gen, one of it's output is simulation script file for functional simulation but i don't now how can i simulate the core functionality using this script in modelsim. do i must create a new project in modelsim and add the testbench files? In ug343 it...
  10. jason_bill

    is implementation of jpeg 2000 resnable as MSc thesis?

    thanks BradtheRad, but i can't understand your mean! i speak about choose the MSc thesis subject. do you think can i implement JPEG(NOT 2000) on FPGA as regards i have not enough time. BTW,i must read data from pc through PCI Express bus and then send back to it. thanks for your attention.
  11. jason_bill

    is implementation of jpeg 2000 resnable as MSc thesis?

    Hi Is implementation of JPEG2000 reasonable choice as MSc thesis? I searched about it but it seems that information isn't enough. and i think i can't do it in 6 month. - - - Updated - - - What do you think about JPEG implementation? thanks - - - Updated - - - What do you think about JPEG...
  12. jason_bill

    Bulk-driven Current Mirror

    thanks dear erikl, i check the connection of current sources and my connection was true, this is the output of hspice when the ibias=180uA: model 0:p_lv_18_ 0:p_lv_18_ 0:p_lv_18_ 0:p_lv_18_ region Linear Saturati Linear Saturati id -163.3775u -163.3769u -163.1870u...
  13. jason_bill

    Bulk-driven Current Mirror

    Hi i want to simulate this structure : so i write this Net list: .param Ibias1=.3m .param v1=.8v .param v5=.4v *+++++++++++++++++++++++++++++++++++++++++++++++++++++++* VDD 1 0 DC v1 VG 2 0 DC 0 VB 5 0 DC v5 IDSS1 3 0 50U IDSS2 7 0 50U Iin1 33 0 Ibias1...
  14. jason_bill

    digital audio level increment

    here you are :**broken link removed**
  15. jason_bill

    digital audio level increment

    Thanks for reply. yes,I know it's possible with analog amplifiers!!! I want to know is it possible to increase the "digital" audio level in digital manner? in my research on internet i found it that it possible by multiple the audio sample with logarithmic factor this means we must convert...
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