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Dear analog experts, can someone comment on typical IO pad speed at low voltage (0.9 voltage), c90lp technology, and low-power IO let's say?
What would be a decent output delay I should expect, in worst case, 60 degree C, with 0.9v or 2.6v IO supply?
0.9v -> 50ns, 2.6v -> 10ns?
Re: negative timing check
Is there a way to disable $width timing check on the FF's ck input?
We have logic designed where the ck can be short pulses, and the FF output corrupts because $width timing is violated, although the d input doesn't change.
We want to prevent X propagation in this...
The two clocks from the PLL are orthogonal, i.e. one of them is 90 degree away from another. So XOR-ing them will get a 2x clock w/ good (not perfect) duty cycle. If we don't do it this way, we would need a PLL w/ 4x VCO and devide it down by 2 to get a 50-50 clock. Then the PLL divide ratio is...
In our project we have a PLL which outputs two clocks and they are XOR-ed to generate a clock with 2x higher frequency. When we do STA, we have problem because when creating generated clocks doubling clock isn't supported, so we can't get the delay from PLL and through the XOR gate propagated...
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