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I did the changes with regard to the statements and the logic and this is what I have. But I am getting an error which I am unable to solve.
module fsm_model(clk,t,r,k,rst);
input clk,rst;
input [16:0] t;
input [16:0] r;
output reg [16:0] k;
reg state;
reg [16:0] g;
reg [16:0] h;
parameter s1...
I have tried to replace the while with a FSM model. But not successful in doing so. The output which is k is not passed to the output port.
1: while T[16] = 1 do // if (MSB bit of T==1)
2: T[16] = 0 //set the MSB bit to 0
3: T = T + (2**16 mod Y ) //and a precomputed...
Hi,
I am trying to implement a particular algorithm in verilog whose pseudo code is given below. I have problem with the while loop(LINE 7 & 11). I get this error when the while loop is used; Non-constant loop condition not supported for while. Can someone suggest me an alternative.
Compute...
The result of t0 which is r[i+1], I need to check if it is even or odd and the do the respective computations. Since f is 8bit, I cannot declare it as genvar . It again causes error.
The algorithm:
Z=0;
for (i=0;i<n;i++){
{Z=Z+j[i]k;}
if (Z%2=1)
{ Z=Z+M;
Z=Z/2;
}
else
{Z=Z/2;}}
if (Z>M) {Z=Z-M;}
The code i have written is as:
module monto_arithmetic(j,k,n,y);
input [7:0] j,k,n;
output reg [7:0] y ;
wire [7:0] p [0:7];
wire [7:0] r [0:8]...
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