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Recent content by jasensio1

  1. J

    Mosfet failure (Drain-Source shorted)

    Hi FvM. I missed that Vgs little detail. Good point. I assume there are some significant transients on Q43. I need to do some more testing. The battery is never disconnected. I also found something but not sure is it is enough to damage the transistor. When 12V rail is enabled, Q23B/Q24B are...
  2. J

    Mosfet failure (Drain-Source shorted)

    Hello everyone. I´m having problems with switching mosfets. Some of them appear to be damaged after some time, staying in ON state regardless control signal state. The system is powered by a 7.2V lithium pack. 3V_2 rail is used to power an SD card. 12V rail is used to power 2 current loop...
  3. J

    VIH and VOH: How can I deal with them?

    Hello. The point is that I am facing 2 main problems: 1) My system is battery powered, so I need low power stuff, 2-3 uA quiescent current as maximum in stand by mode. 2) The line I need to adapt is a serial bus running up to 115200 bps, so I can't think about a transistor based solution which...
  4. J

    VIH and VOH: How can I deal with them?

    Hi Klaus. This is the graph showing driver VOH, for Vcc = 3.3V. So here is the main question...VOH is a consequence of output current only, because output impedance I guess?
  5. J

    VIH and VOH: How can I deal with them?

    Hello guys. I've got a driver running at 3V and a receiver running at 3.3V. According to datasheets, these are threshold values: Driver: VOH 2.4V min (4 mA) Receiver: VIH 2.5V max. Input max current 0.5 uA First thought is that they are not compatible but, are variations between min...
  6. J

    [SOLVED] Remove via pads on external layer

    Hello everyone. I have a 4 layer pcb with high speed signals routed on layers 1 and 2, so I'd like to remove unused via pads on layers 3 and 4. If removing the via pads on layer 4 (bottom layer)...would the holes be properly plated or could it cause a manufacturability issue? Thanks!!
  7. J

    Unterminated RS485 bus

    Hello guys. To improve power consumption on a battery powered system, I am planning to remove the termination resistor on a RS485 bus. It will carry point to point communications (just two transceivers attached to the bus) at low baud rate and through a short cable (2 meters long). I am using...
  8. J

    impedance control with mixed laminate

    So... Should I rely on them to get the pcb's built without requesting layer stackup details from them previously? What is the common practice? Regards
  9. J

    impedance control with mixed laminate

    impedance control with different prepreg styles in a dielectric Hello guys. My layer stackup looks like the picture Lets say that: - Dk for 2116 is 3.4 - Dk for 7628 is 3.7 I need a 50 ohm impedance in layer 1 (layer 2 is ground). For impedance calculations, how do I manage two different...
  10. J

    Any obvious issue with this layout?

    Thanks for your responses guys. What do you think about track width-component pads difference? Regards
  11. J

    Any obvious issue with this layout?

    To be honest I don't know
  12. J

    Any obvious issue with this layout?

    Hi guys. I'd like you to have a quick look at the pics and leave a comment... It is part of the RF section of a system with GPRS/3G communication capabilities. The pcb layout shows a transmission line with a track width that is a bit narrower that component pads connected to it... is this...

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