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I didn´t understand your message. Please allow me to do it.
First, I will describe a little more about the code I posted. If you already understood and your comprehension about it is the one bellow, sorry and please disconsider it.
The idea behind my little...
Please consider a VHDL module which must behave according to the following scenario (clk = clock input; rst = assynchronous reset):
1) clk, rst --> module --> n-position vector with m-bits
2) n: I need sizes such as 20, ..., 50;
3) m: something like 4 or 8 bits...
I consider the web discussion forum one of the most important sources of solving problems which the documentation is not clear.
In this aspect, I consider Xilinx forum contaminated with CB-cyberbullying (with emploees following what is happening). In Altera forum I didn´t see CB.
Hi Tricky,
Thank you. Codes 2 and 3 did run fine.
Here is a fix in code 2, inspired on your hint, to allow f_clk express the desired frequency to be generated (now using your suggestion about code presentation here). This fix was also used in code 3.
library ieee;
use...
Hi Tricky,
Fisrt of all, thank you for your reply!
Yes, I suspect that I will be a beginner forever... :)
I was reading exactly about signals vs variables (PEDRONI, 2010, p. 177-198). There is a full chapter to treat the differences between them. Obviously I am making a mistake that...
Hi,
I need to build in VHDL a clock generator.
The inputs and output of my circuit are:
input reset ('1' sensitive);
input master clock (Digilent Basys 2 board oscilator); and
output clock.
I present to you two versions of my vhdl code. One with shared...
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