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Jansi Meena

Recent content by Jansi Meena

what is the direct definition of primitives at fpga ... ?

Is primitive components always be same for all devices?. Also, to simulate, does it require special attention?.
- Jansi Meena
- Post #6
- May 8, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Little endian to Big conversion, simulation results are not clear..?

Thanks, most of the devices, like some Ti DSP I've worked, is in big endian only. This is what they used for SPI, other communications... What is it to have problem with read-order?. In VHDL I find is no trouble in switching between Big\Little endian....
- Jansi Meena
- Post #14
- May 8, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
how to divide a number by 1000 in FPGA

IN VHDL\Verilog is divisor allowed?....All I know is repeated subtraction for division in case of integers not in power of 2
- Jansi Meena
- Post #3
- May 8, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Little endian to Big conversion, simulation results are not clear..?

yes, it is supposed to be "downto". Thanks friends. One more doubt, is endian not applicable for bitwise?.
- Jansi Meena
- Post #6
- May 4, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Little endian to Big conversion, simulation results are not clear..?

OMG, the code is useless?. I never thought that way. Then I wonder why it has been used in many places.... So even if I pass a value from "downto" to "to", the integer or number wont change?. Please clarify me, as I am greatly confused.... For eg, this is just for my clarity and the code is no...
- Jansi Meena
- Post #3
- May 3, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Thanks Tricky
- Jansi Meena
- Post #22
- May 3, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Little endian to Big conversion, simulation results are not clear..?

Please help me, I have got this file, which they say it converts little to big endian. One module I have gives data in (0 to 33) and another module has (33 downto 0) data type. I've been told that the below code will do the convesion entity le_2_be is port ( ARRAY_IN : in...
- Jansi Meena
- Thread
- May 3, 2012
- Replies: 14
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Also, (-8 to 7) is indexed -8 to 7 only but this is just equivalent to raw 16 bits still, the neg index is just for the convenience?. For the Hardware logic, 0 to 15 or -8 to 7 is no different?
- Jansi Meena
- Post #20
- May 3, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Yes, but what exactly i am asking is like this statement allowed for synthesize? data <= my_array(-5)
- Jansi Meena
- Post #16
- Mar 20, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Thank you....
- Jansi Meena
- Post #14
- Mar 19, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Thanks for the brief. But this is the first time, I'm heard about neg index in array(-8 to 7). What's the use?,is it synthesizable? too?
- Jansi Meena
- Post #12
- Mar 19, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Thanks, I got it. Now one more doubt. If I declare in any of my array declarations as (NATURAL RANGE <>) instead of (1 to 8) or some finite length what happens?. How much depth my signal will get in such case?. I can not see any range in this (NATURAL RANGE <>). HOw does the tool guess the...
- Jansi Meena
- Post #10
- Mar 19, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Oh...I've thought this is array Type a is array (1 to 8) of std_logic_vector(7 downto 0); signal x : a :=
- Jansi Meena
- Post #8
- Mar 19, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Thank you. But why do you say this signal a : std_logic_vector := "00000000"; as Array?... It is an eight-bit signal right. I have not type declared it as array...Pls can you explain?
- Jansi Meena
- Post #6
- Mar 19, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Oh sorry Tricky, this seems to be for constant, I just mis-typed.Thanks Constant a : std_logic_vector:="00000000"; However in this case, what will be the format of the constant 'a' Is it "downto" or "to" Thanks
- Jansi Meena
- Post #3
- Mar 16, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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Jansi Meena

Welcome to EDAboard.com

Recent content by Jansi Meena

what is the direct definition of primitives at fpga ... ?

Little endian to Big conversion, simulation results are not clear..?

how to divide a number by 1000 in FPGA

Little endian to Big conversion, simulation results are not clear..?

Little endian to Big conversion, simulation results are not clear..?

[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

Little endian to Big conversion, simulation results are not clear..?

[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

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