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Recent content by jamesr

  1. J

    ADC to DAC Bit conversions

    Hi Barry, I see, that does seem a sensible thing to do. Thanks very much for the help, seems quite clear now on what I need to do.
  2. J

    ADC to DAC Bit conversions

    Hi Barry, Yes, essentially that's what I was thinking, the sum of 2 10bits can't exceed 11 bits so I can send this straight to the DAC. If I was then to use a different filter, say 3 or 4 point, it could be possible to have an overflow from the 12 bits, but my thought is to still do a shift...
  3. J

    ADC to DAC Bit conversions

    Hi, I have a requirement (well assignment) to sample some data from a 12 bit ADC into a 10 bit word, then do some filtering, then pass this back to a 12 bit DAC. Quantising the 10 bit word form the ADC from what I can read is just a simple as shifting the bits and losing the LSB's. (Correct...
  4. J

    [PIC] Nested Delay Loop Theory

    Hi, Yes I am using MPLAB. I had a go through the data sheet and count them up, I calculated 7 cycles for a complete loop round to the start of each cnt decfsz. I will run MPLAB stopwatch and see what figures I get at each breakpoint for the counters. - - - Updated - - - Thanks for these, that...
  5. J

    [PIC] Nested Delay Loop Theory

    Yes, I understand that; I have factored into the math the "7 machine cycles" that each loop takes. Based on the data sheet for a PIC16F877A. Can you expand on what you mean in relation to my question about the calculations? Thanks
  6. J

    [PIC] Nested Delay Loop Theory

    Hi, I have looked around at Delay examples and many of the forums suggest using a nested loop to create large delays. Most of the forums point to a Delay generator tool which creates the code for you based on the clock freq and delay. This is great for implementation but for those of us...
  7. J

    [SOLVED] Binary Counting on PORTB to 255, PIC16

    Hi, Thanks for the all the help, wp100 you were right about the debug on the board, it turns out there was a jumper setting for ICD that needed to be disconnected once programmed. Not obvious in the use guide either so just by trying different switches I got it to work. Many thanks.
  8. J

    [SOLVED] Binary Counting on PORTB to 255, PIC16

    Hi, Thanks for trying the program, yes I've moved the PORT to D and it's working ok. Seems there must be something with the eblocks that I need to figure out. I thought the debug off command should have done something but it hasn't. I can run it on PORTD fine, just need to find out what the...
  9. J

    [SOLVED] Binary Counting on PORTB to 255, PIC16

    list p=16f877A ; list directive to define processor #include <p16f877A.inc> ; processor specific variable definitions __CONFIG _CP_OFF & _DEBUG_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _HS_OSC & _WRT_OFF & _LVP_OFF & _CPD_OFF ; '__CONFIG' directive is used to embed configuration data...
  10. J

    [SOLVED] Binary Counting on PORTB to 255, PIC16

    I think the semicolon depends on the compiler you are using. I have not posted the full code, yes there is a start/end. The code above works, as in compiles and makes most of the LED's light up. I think the point here is about configuration of the PINS on PORTB that I'm not aware of? Would...
  11. J

    [SOLVED] Binary Counting on PORTB to 255, PIC16

    Thanks, in order to simplify the program I have used the below just to light up all LED's on all the ports as a test. However I get the same issue. When you say the Pins have other options, from what I understand the TRISB command sets all PORTB pins to output. The data sheet states the pins...
  12. J

    [SOLVED] Binary Counting on PORTB to 255, PIC16

    Hi, Probably a simple question, but I have written a program to count in binary (i.e. output to LED's on PORTB) which is fairly simple and counts from 0 to 16. This works fine in simulation and when programmed onto a PIC16F877A running on a multi matrix eblocks device. I.e the LED's count up in...
  13. J

    VHDL generate port map issue

    Thanks, I finally got it to work. I had the signal declaration for the internal link inside the for generate loop, I moved this outside into the architecture body and its working. Thanks for the clarification on the If statements though. J
  14. J

    VHDL generate port map issue

    Hi, I have the code below which as far I can work out should be connecting a number of components together in a chain, a bit like a ripple carry, but this for a comparator, with MSB first. Is the syntax correct because it does work, if I synthesize the code to see what circuit I get, it seems...

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