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Re: fpga cpu
The J1 is a very small FPGA CPU with memory, stack, etc, in under 200 lines of Verilog. The version here:
The J1 Forth CPU
also has a VGA display interface.
Here is how I do it using Python to generate the table, using an initialized Xilinx RAM64X1S to hold the values. It is in Verilog, but converting it to VHDL should be easy.
RAM64X1S as a sine wave ROM
Re: generating clocks using vhdl
This page explains fractional clock division, and gives the VHDL and Verilog to do it.
Making an arbitrary frequency clock in VHDL and Verilog
in this case your input frequency is 80000000 and output frequency is 2048000.
You can derive the 64KHz from the...
A good place to start is an evaluation kit, there is a list here:
Summary of FPGA development boards - excamera
On clocks: modern FPGAs have clock multipliers, so you can use a board with a fixed frequency, say 25MHz, and generate the higher/lower internal frequencies you need.
This page...
Converting a number to a float in VHDL is not very hard. You need to compute a sign, mantissa and exponent:
take absolute value of number, set the sign bit if it was negative
left-justify the number; this is the mantissa
the exponent is the distance shifted in step (2).
Re: Ethernet with FPGA
Best bet is to make an ARP request packet. Construct an ARP WHO-HAS packet asking for the laptop's IP. The laptop will respond with its own ARP. After you have ARP running, ICMP (PING) is next.
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