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Hi,
On what basis is the cell row height fixed in the semi custom physical design. Since the length of the transistor is based on the technology, and the width could vary if the nmos or pmos is fingered, the cell row height cannot be completely based on these. So which factor of the standard...
Hi,
I would like to know which all metals are used in each routed layer while fabricating the ICs. As the power and ground nets are routed in the higher layers where the resistance is less, I guess different metals are used for different layers.
Can somebody please throw some light upon...
Hi,
thanks for the info. However I would like to know a few more things. Will it be possible for a verification engineer to switch to RTL design afterwards?
Can verification engg go to the extend of becoming a project manager?
I have heard in India few verification engineers are switching...
Hi,
Whats the scope of jobs in functional (RTL) verification in VLSI? From what I have heard from my friends and other people, verification jobs become kind of boring after a couple of years. Its just passing the test cases and verifying the RTL since the same environment can be used for...
Which domains have more opportunities, the back end (Physical design, analog layout etc) or front end (RTL design and verification)? Would like have an expert opinion in this before I chose my field.
(Which domain has more opportunities in Indian market too)
Thanks
Hi, I have a very basic question. I m sure this would have gone through most of the people's mind.
All knows what are set up and hold time and what all would happen when they are violated. But, when we consider a master slave latch, (i.e constructing blocks of a flip flop) , where is the actual...
msc project log
Hi,
Need help in identifying a suitable project in ASIC domain that is quite relevant to the current industry. Communication, processor, networking, protocols etc would be good. If possible kindly help me out with some links.
-Thankyou
one reason i know is that since latch is level sensitive, the output could come at any point of the particular level. Hence it could lead to the formation of glitches.
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