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Recent content by jagansai

  1. J

    use of for loop in vhdl

    can you tell the diff between this two assignments if( rising_edge(clk))then d_in(width-1 downto 0)<= d_out(width-1 downto 0); end if; if(rising_edge(clk)) then for i in 0 to width-1 loop d_in(i) <= d_out(i); end loop; end if; sorry i entered wrongly. Now,i enter correctly. my question is...
  2. J

    use of for loop in vhdl

    can you tell the diff between this two assignments if( rising_edge(clk))then d_in(width-1 downto 0)<= d_out(width-1 downto 0); end if; if(rising_edge(clk)) then for i in 0 to width-1 loop d_in(i) <= d_out; end loop; end if;

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