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Recent content by jadedfox

  1. J

    does warning as combinatorial loop allow simulation to run?

    simulation... Is warning as combinatorial loop doesn't allow simulation to run?
  2. J

    output signal as input (feedback) in verilog

    Re: feedback input The module i posted earlier is the top module. Here's the rest of the part..... //////////////div_10///////////// module div_10( enable, in, out ); input enable, in; output out; reg out; reg [3:0] cntr; initial begin cntr <= 4'b0000; end always @( posedge...
  3. J

    output signal as input (feedback) in verilog

    Re: feedback input thnx for replying,, i'm using dco_out as feedback but these are the warnings i got---
  4. J

    output signal as input (feedback) in verilog

    Re: feedback input thnx fr d reply... ya i ll try that... but can u explain the last line that u wrote. btw i'm doing this on a fpga chip... so i ll not be doing P & R
  5. J

    output signal as input (feedback) in verilog

    Re: feedback input I did it as you said but it's still giving me warning.. I need to have that combinatorial loop in my design, will it cause any simulation issues.. anyways here is how i did-- module adpll ( ref_in, en, rst_n, dco_out ); input ref_in; input en, rst_n; output...
  6. J

    output signal as input (feedback) in verilog

    Re: feedback input no,, it did't help... can any one suggest any other way of doing it....[/b]
  7. J

    output signal as input (feedback) in verilog

    feedback input In verilog, how can we giv output signal as input(feedback).. like in case of a digital pll output of pll is fed back as input... I think the synthesis tool gives a warning as "combinatorial loop.." how to model it without any warning?
  8. J

    need explanation-situations 3-state aren't replaced by logic

    3-state is it correct or some mistake is there in it? if correct, can any 1 explain me wht it means? taken from-
  9. J

    Help me remove some XST warnings

    xst:2042
  10. J

    How do "bufif0" and "bufif1" in Verilog HDL create warning in synthesis?

    bufif verilog any one....
  11. J

    How do "bufif0" and "bufif1" in Verilog HDL create warning in synthesis?

    How do "bufif0" and "bufif1" in Verilog HDL create warning in synthesis? how does in Verilog HDL "bufif0" "bufif1" creates warning in synthesis? when can/should they be used to avoid warning?
  12. J

    Help me remove some XST warnings

    module dig_cntrl_osc(enable, DCO_CONTRL, DCO_OUT); input enable; input [7:0] DCO_CONTRL; output DCO_OUT; not invsel0( CONTRL6b, DCO_CONTRL[6] ); not invsel1( CONTRL7b, DCO_CONTRL[7] ); and andsel0( sel0, CONTRL7b, CONTRL6b ); and andsel1( sel1, CONTRL7b, DCO_CONTRL[6] ); and andsel2(...
  13. J

    xilinx - need help in debugging a code

    Re: debug... I didnt get any such logs.. in the synthesis report -- about specify block -- about enable of div_10 however i did get logic pull-up msgs..
  14. J

    xilinx - need help in debugging a code

    Re: debug... thnx fr ur reply... i ll see into it but can u plz tell how...is that??
  15. J

    xilinx - need help in debugging a code

    Re: debug... any one...
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