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Recent content by jackrc11

  1. J

    How to properly short together named nets for schematic and layout (Cadence Virtuoso)

    I'm trying to short together multiple named nets in a digital bus- previously when I was just testing on a schematic level, I used 0 ohm resistors from the analoglib library, but as I'm now working on layout (tsmc 65nm), this isn't an option. Is there a specific block or layer used to do this...

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