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Recent content by jackeeer

  1. J

    Fractional Frequency divider using Sigma Delta Modulator

    Ok, so from your explanation the second order sigma delta (used in fractional divider) should have 2 bits output that will change between following states :{-1, 0, 1, 2} but there is a lot of examples of 2nd order sigma delta that has 1 bit output. SO What are they use for? Are they used only...
  2. J

    Fractional Frequency divider using Sigma Delta Modulator

    Thank you for your honesty. Correct me if I am wrong: Does your explanation correspond to MASH type of Sigma Delta ? If I understand you I can use only 1st order sigma delta for Dual Modulus Divider...For higher orders I need to use MULTI modulus divider that has multi bits control...
  3. J

    Fractional Frequency divider using Sigma Delta Modulator

    Yes, this is 1 bit output SDM. I use it to investigate on SDM working and noise shaping. As I posted at the begining of this thread I see the noise shaping at the SDM output. I've thought I can use it to control Dual Modulus Divider (n or n+1) and would see the noise shaping...Is there a chance...
  4. J

    Fractional Frequency divider using Sigma Delta Modulator

    Thanks for your reply pancho_hideboo, It seems I need to read more about SD modulators. I thought my dividing ratio will be purely N or N+1 depending on sigma delta output signal - high or low. I am using following verilog-A code for 2nd order SD modulator. Please look. analog begin...
  5. J

    Fractional Frequency divider using Sigma Delta Modulator

    I meant "Moreover for HIGHER div ratio I need to make my simulating longer..." YES, I am familiar with those two concepts however it is first time I do something with sigma-delta modulator and factioanal dividing. So far I have used 10 MHz and 100 MHz as divider clock input and mostly 20 KHz...
  6. J

    Fractional Frequency divider using Sigma Delta Modulator

    Can you please tell why I need to increase it instead of saying I need to do it? For higher dividing ratio the output has too low frequency in compare to sigma delta output - this is why I did not want to do this. Moreover for lower div ratio I need to make my simulating longer... I can...
  7. J

    Fractional Frequency divider using Sigma Delta Modulator

    Thanks for help. I did another simulation for 10 ms, fin 100 Mhz, div by 3 or 4. I have got following results: Has anybody know why cant I see the peak at frequency (100MHz/3.5 (3.5 is div factor) ) and the noise shaping? Regards, jackeeer - - - Updated - - - One more question: Does my...
  8. J

    Fractional Frequency divider using Sigma Delta Modulator

    Thanks for your reply pancho_hideboo, Can you point the place where you see the noise shaping at my printscreen of freq divider output? I understand the noise may be shaped not so efficient like at the modulator output but I have expected it shape will be similar. I found some publicaton...
  9. J

    Fractional Frequency divider using Sigma Delta Modulator

    Hello everyone, i am working on sigma delta modulator that I need to use in the fractional divider. Like for now I am facing the noise shaping phenomena and I do not understand one thing... Let me describe the problem: I know why the noise shaping occurs in sigma delta and can see it in the...
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