Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by ismailov-e

  1. I

    ADMA on SD Host Controller

    Guys it seems I understood: The driver puts initial address to the ADMA System Address to point the initial line of descriptor. The Host Controller using those address from the ADMA System Address directly gets a descriptor from the system memory and increment an address to take a next...
  2. I

    ADMA on SD Host Controller

    Hi everybody!! I am writing ADMA FSM in SD Host Controller. The Host Controller has ADMA System Address that uses as a pointer for Descriptor table of System Memory. In specification they are explained that one descriptor line consumes 64-bit (8-byte) memory space, 63-32 is address; 31-16 is...
  3. I

    Pl and Peripheral interaction on Zynq SoC

    Hi everybody!! How can we read USB flash or other peripheral from PL side directly (does not involve CPU or DDR)on Zynq SoC? Can we use usb2.0 IP in this situation and what about File system?
  4. I

    Alternative(optimum) usage of memory in FPGA.

    What you mean under the code is not written correctly?
  5. I

    Alternative(optimum) usage of memory in FPGA.

    As an example above I putted (* ram_style = "block" *) in one of the source file . After synthesis is still using "distributed" not "block" ram (BRAM). Also i have a question: If i have 3 source files of different slave ports, does this label (* ram_style = "block" *) putted on one of the source...
  6. I

    Alternative(optimum) usage of memory in FPGA.

    I tried to use BRAM in custom IP but couldn't. Is there any trick? In simple source file it is changes.
  7. I

    Alternative(optimum) usage of memory in FPGA.

    I have declared the 2d array regester as: (* ram_style = "block" *) reg [15:0] state_machine [0:state_count][0:96]; - - - Updated - - - I have checked with 1D array and it's works fine(programm below), but with 2D it not. /* ** This example shows the use of the Vivado ram_style attribute **...
  8. I

    Alternative(optimum) usage of memory in FPGA.

    https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf#M5.9.55876.Heading2.ROM.HDL.Coding.Techniques But I found here: Vivado synthesis can interpret various ram coding styles, and maps them into Distributed RAMs or Block RAMs. - - - Updated - - - Also...
  9. I

    Alternative(optimum) usage of memory in FPGA.

    Hi! Are all registers, array or matrix of registers are uses DRAM memory? I have used a 2D array of register with 32 bit cells, and the utilization exceed maximum FPGA's (Zynq7020) possibilities(LUT and FF), but BRAM,MEMORY LUT, DUFG has shown less usage. Is there any solution to use BRAM?
  10. I

    Direct assignment to matrix in Verilog.

    Thanks for your reply. Is this syntax in System Verilog? I have an error in Verilog.
  11. I

    Direct assignment to matrix in Verilog.

    Thank you. But language there is VHDL and no assignment shown.
  12. I

    Direct assignment to matrix in Verilog.

    Hi everybody! Can we assign matrix directly like in C language. For example: reg [7:0] matrix [4:0][4:0]; matrix = {12345,54321,23432,55533,22212}; or matrix = {{1,2,3,4,5},{5,4,3,2,1},{2,3,4,3,2},{5,5,5,3,3},{2,2,2,1,2}}; - - - Updated - - - After Synthesis the message come: "[Synth...
  13. I

    Printf all memers of structure.

    Thank you for your reply. But I tried avoid to write all members as you did. And after I aimed to write to file. I succeed with "fwrite" function. fwrite(&book,sizeof(book),1,f);. But it is write to file the value of members in disorder.
  14. I

    Printf all memers of structure.

    Hey. I found how to do this. Using Binary I\O Functio. I have one question: Can I write members in file separeted with new line?
  15. I

    Printf all memers of structure.

    Hi everybody!! How can I use only one printf to print all memers of structure. For example: #include <stdio.h> #include <string.h> typedef struct Books { char title[50]; char author[50]; char subject[100]; int book_id; } Book; int main( ) { Book book; strcpy(...
See more

Part and Inventory Search

Back
Top