Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by ise_lewis

  1. I

    Why is this constraint violated?

    I use the following constraints : set_clock_uncertainty 0.2 [find clock scl1] set_clock_latency 0.5 [find clock scl1] set_clock_transition 0.5 [find clock scl1] constraint report the violations min_delay/hold ('scl1' group) Required...
  2. I

    Problem with a I2C slave circuit simulation

    Re: I2C problem I think the causes : 1. Timng constraint, How to constraint dual-edge clock of I2C? 2. I2C Pad, anyone give me a schematic of a I2C pad with ESD?
  3. I

    Problem with a I2C slave circuit simulation

    Re: I2C problem run at 100KHz - 200Khz. It is not quick.
  4. I

    Problem with a I2C slave circuit simulation

    My design is I2C slave circuit, it latch data by pos-edge of SCL and output by neg-edge of SCL. I run simulation post-synthesis with Modelsim, it is ok. And then I generate cdl file from nestlist with CMOS models, but when I run simulation with HSPICE, it is wrong. When it send ACK bit , SDA...
See more

Part and Inventory Search

Back
Top