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Yeah, I know it doesn't use the dff as a component, it's just a second way by modifying the dff code as you and BlackHelicopter suggested.
Thx again :)
Thank you very much Kevin Jennings, I think I understand now how it works, and the simulation is running smoothly, according to the vhdl code :)
@BlackHelicopter: Yes, clear and preset are asynchronous, and the parallel load is synchronous i suppose, the assignment does not specify it.
These...
Thank you very much for your answer, you have been very helpfull! I have 3 questions however:
1. D_sig1 <= D when (Load = '1') else Q_sig;
I suppose that D_sig1 is Q_sig and D is D_Sig right?
2. in the port mapping, you set 'clear' to 0, according to the D FF I've posted, if clear is '0'...
Hello everyone,
I am new to VHDL and I have to write behavioral vhdl code for a 4-bit register with parallel load, using a D-Flip Flop. Here is the D-FF code i have to use:
library IEEE;
use IEEE.std_logic_1164.all;
entity dff is
port (d : in std_logic;
preset : in std_logic...
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