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Recent content by inquisitive

  1. I

    Meaning of Mask type : ASF/ DSF

    In the Design Rule manual released by founderies, the mask type for some layers is indicated as ASF, for others DSF. That does this (ASF/DSF) indicate?
  2. I

    Buffer: coupling from output to input

    I have to design a buffer which buffers 0.6V voltage (which is coming from Bandgap ...) to some other block. Any noise/ sudden variation at the output should not affect the input of the buffer. what do I need to consider in my design (not layout), to make sure that this noise doesnt reflect at...
  3. I

    what forms the channel in a MOS

    Say V(S)=V(D)=0, VGS>VTH. My doubt is : What forms the channel? Are the electrons that form the inversion layer generated by EHP in the substrate? or they are injected from the source? I didnt find the exact answer in any text book. Please help.
  4. I

    what is polymide layer?

    what is polymide layer? Is it the same as gate POLY?
  5. I

    minimize drain or source capacitance?

    Given an option that you can minimize either drain or source capacitance, which capacitance would you minimize and why?
  6. I

    difference between the indian and international editions?

    Hi all, Is there any difference between the indian and international editions of books in VLSI field? Thanks
  7. I

    Regulator to reduce supply noise to VCO??

    the supply voltage is 3.3V+_10%= 3to 3.6V The VCO can work in worst case till 2.8 V. Could you plz elaborate on the the scheme for contrl voltage regulation? thanks
  8. I

    Regulator to reduce supply noise to VCO??

    Thanks rfsystem, since i have almost no headroom for a series regulator, have ever used a shunt regulator? thanks
  9. I

    Regulator to reduce supply noise to VCO??

    I have a PLL diesign with a ring oscillor (CMOS) already in place. I want to put a regulator to reduce supply noise to VCO. What regulator configuration should i use? I cant have much voltage drop on the regulated voltage so that my VCO works correctly. I cant use use an LDO since i cant use an...
  10. I

    How challenging is it to design a PLL with 50ps Jitter and 100MHz clock output?

    Re: PLL Design I have a PLL diesign with a ring oscillor (CMOS) already in place. I want to put a regulator to reduce supply noise to VCO. What regulator configuration should i use? I cant have much voltage drop on the regulated voltage so that my VCO works correctly. I cant use use an LDO...
  11. I

    book for I/O (input buffer) architectures and issues

    Hi all, can u suggest some good book for input buffer architectures and issues related to them. I have to design a clock input buffer and want to know the issues that may arise.
  12. I

    Layout questions about widths and resistors

    Re: layout question Vamsi, what are these metal options that u were talking about? when and why are they used?
  13. I

    to determine noise margin????

    determining noise margin from inverter simulation How do we calculate noise margin of any circuit say a inverter bu simulation???
  14. I

    Beginner in analog circuit design

    beginners circuit design hello everybody i feel this question has been asked too many times on this forum. people should search the forum first before puttong such questions. inquisitive
  15. I

    Analog designing in I/0 ?

    Re: analog deisgn in I/0 thank you all , particularly Btrend. I am a fresher and have got job offer in i/o. i like analog, but do not know what exactly will be my work in analog? can i call myself analog engineer after i work in i/o?
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