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Recent content by incisive29

  1. I

    Need Help regarding Actel FPGA Area Constraints

    This is precisely what I mean. I did mention negative slack earlier. Anyway, thnx for the links.
  2. I

    [MOVED] Fetching Pdb files from Actel FPGA

    Re: [MOVED]Fetching Pdb file from Actel FPGA Kindly let me know if there is a pdb file extractor in case of FPGAs. Please elaborate on source control.
  3. I

    [moved] CLKBUF and INBUF actel FPGA

    Thankyou for your reply. When I remove inbuf, the design synchs out. I think I should stick with my current macros.
  4. I

    Timing Constraints for external clocks

    Can you please elaborate on what is wrong? I have defined the clock in sdc. On running synthesis, I am getting negative slack on this clock. Is there some other method of defining them?
  5. I

    Timing Constraints for external clocks

    Basically I am receiving external seial data at 6MHz clock through a MicroD9 connector. Then I am writing this data coverting into bytes into FiFOs using the same clock as my write clock and a strobe signal associated with each byte as my Write enable. Reading is done at 12.5MHz. This 60MHz...
  6. I

    Timing Constraints for external clocks

    How do I add input delays when using external clocks in Actel FPGA. Because when I apply clock contstraints to external clock, negative slacks are produceds.
  7. I

    [moved] CLKBUF and INBUF actel FPGA

    When and how to use CLKBUF and INBUF in actel FPGA? When I use CLKBUF in my program, it gives error. I replace it with INBUF, it works fine. What I read in an application note was CLKBUF is used when a clock needs to be be mapped to multiple modules,that is high fan out. whereas INBUF has only...
  8. I

    [MOVED] Fetching Pdb files from Actel FPGA

    [MOVED]Fetching Pdb file from Actel FPGA I have two boards with Actel FPGA Proasci3 A3P1000 mounted on it. I programmed board A with a pdb file. The program runs fine, even after giving multiple power cycles. Now I want to program board B with the same pdb file. How do I fetch the pdb file from...
  9. I

    Need Help regarding Actel FPGA Area Constraints

    I want to know how do you add "input delays" to the external clocks which are the cause of negative slack in the design? What parameters should i consider for calculating input delays for my external clock to remove slack?
  10. I

    packet formation and convolution coding..single ended to external lvds on actel fpga

    Hi.. I have designed a program which packetizes data and performs convolution coding in actel fpga A3P1000, i have converted the single ended output i q and clk to differential output within fpga, the program runs fine. On the second board I then used the single ended output and used an...
  11. I

    how to use 2 clock (PLL) cores simultaneously on Actel FPGA ProAsic3E A3PE1500

    Hi I am using actel's starter kit. with ProAsic3E A3P1500 PQ208 FPGA. I have a program in which I am supposed to produce 3 clocks, one of 150MHz. 112.5MHz and 14.063MHz. Since i can't produce all three using one CCC core, I generated 112.5MHz and 14.603MHz in one core using CLA as hardwired...
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    MM74C922N-capacitor values for osc and kbm

    MM74C922N I'm using MM74C922N with my keypad and the controller used is atmega162. How much should be the value of external capacitors at oscillator and KBM (keybounce mask)?
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    LCD programming on assembly.

    i want to program 2*16 LCD on assembly language for my project electronic voting machine. Controller used is avr at-mega16. there are 5 candidates and a total of 20 votes possible. every candidate is assigned a register and the value increments if the candidate gets a vote. i want to display the...
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