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Recent content by ilter

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    Tutorials and materials about SAR ADC

    Re: SAR ADC Question Dear all, I design my sar adc. My input is signal-end. My (p) input's common mode is 0.425V and my peak-to-peak is 0.8V. In the chip, my (n) input is 0.4V so the input has some offset. I run simulation and my comparator's input's ENOB is bigger than 4.5. But my...
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    Measure DC to DC converter

    Dear all, If my bulk's waveform's voltage is correct, the frequency is not correct. Why? It's voltage is 1.8V. But the frequency is strange and it is not a stable frequency. Thanks.
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    Measure DC to DC converter

    Dear all, I measure my dc to dc converter ( 3.3 -> 1.8 ) . My design is load current is 0.8A. But I measure my output will have a spike at load current of over 0.4A. This spike will be sometime the peak of 2.8. This condition my OCP is off. Why do my load current can not over...
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    Help me understand two equations for current DAC design

    Dear all, I design current dac. But I don't understand two equations. What's its meaning? These are the same or double. And I design latches, my power is use digital power. How do I simulate clk jitter? If my digital power is dirty, how do I do? Thanks.
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    Question about sample and hold for capacitor

    Re: sample and hold Dear sir, I change singe input to differentail. I run SNDR in FF is less than in TT. I don't know why? Thanks.
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    Question about sample and hold for capacitor

    Re: sample and hold Thanks very much. My sample and hold is used the SAR adc. I have three question. 1.This adc is 5 bits. ENOB is bigger than 4.5. But I run the cornor of FF , the ENOB is less than 4. But my sample and hold's output's SFDR is larger than 40dB. Why? 2.How do I simulate my...
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    Question about sample and hold for capacitor

    Hi, I am doing sample and hold. I think capacitor question. I have some questions. which one is correct ? why? What is bottom plate? Thanks.
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    Analog question about adc and power on reset

    Dear all, How do I do power on reset about my voltage is 1.2V? If I simulate adc, my input is sine waveform. Is it used ideal waveform? If I want to use the capacitor 100p , how do I used 1p? If I don't used OP, how do I do? Thanks very much.
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    Questions about AD/DA design

    Re: AD/DA design I do pipeline AD , SAR AD , current dac with line driver.
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    Questions about AD/DA design

    Dear all, I have some questions. 1.How do I design my switch of AD? What do I focus on ? Linearity? or... 2.Why do the linedriver use class AB or classA? 3.How do I design common mode feedback? gain , fu or capacitor? 4.How do I desgin linedriver of DA ? Like gain or fu. If you know...
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    Help me understand PFM mode in switching regulator

    Dear all, Which kinds of pfm of swtiching regulator? I want to understand pfm mode. I has some questions. In pmf , if i short my inductor, let output not to ring. How do I do ? Thanks.
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    How to decide on the OP specifications needed for a design?

    Dear all, I have a question. In analog circuit, op is important. Switching regulator and LDO need error amplifier. ADC needs op. How do I calculator or need which kind of op? Like op spec. , gain 、 BW 、CL(output cap) or slew rate? Maybe gain=60 dB or BW = 30M at CL=1u? How do I decide my...
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    Swithing Regulation question

    "A" means error amp and buffer in my picture.
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    Swithing Regulation question

    Dear all, I have some questions. 1.I design swithing regulator.Do buffer need to add between nonoverlap circuit and power mos? 2.How do I decide power mos's length. 3.If I use one regulator and LDO in parallel. Sometimes LDO is on and Sometims SW is on. If LDO is on and SW nmos is off , is it...
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    Questions and problems about LDO design

    Re: LDO question Hello, I design my LDO. My input voltage is 1.8V and output voltage is 1.5V. I find my simulation is in FF , high temperature and high voltage of 2V(input voltage). My output will be 1.78V and not 1.5V. I don't know what's wrong. I think my error amp's gain is not large...
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