Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear Friends,
I'm trying to probe the transient voltage of an internal node in post layout simulation without creating an explicit port on my top level. I used Calibre for PEX. I tried to use the "Map Schematic Nets to CalibreView Net" in ADE L's Calibre drop down menu to find the post layout...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
