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@barry
@dpaul
Sorry, it is my bad for not explaining correctly.
When I instantiate a component like this:
inst_block_x : entity.work.xblock
generic map (
..
..
);
port map (
..
..
);
Will I instantiate the component with the architecture defined in its rtl?
Or do I have to repeat what is...
So, in my project (DUT) we have a down-path and a up-path.
Currently we send specific data (read from a file) as an input to the down-path and we send random data as an input to the up-path.
The problem is that the random data being generated for the up-path didn't quite match a real case...
Hello,
I´m fairly new at VHDL programming language and to the world of Digital Design and Verification and there are some concepts that I still didn´t fully understand.
Currently on my TB I have 8 components, being one of them the DUT.
I have a Testbench (already existing) with different...
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