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Recent content by IceZero

  1. I

    Problem with UART Shifting in 4 bytes

    Re: UART Shifting in bytes Yes this is in the next state logic block (always @*). I think you might be right. Now that I think about it, uart_rx_data_out is of type wire not reg.
  2. I

    Problem with UART Shifting in 4 bytes

    I must be doing something wrong because this isn't working as I expected. What I am trying to do is shift in 4 bytes received from the UART sequentially into a 32-bit register. I've included my code below. When I read back the 32-bit register to the UART, all 4-bytes of the 32-bit register...
  3. I

    An array of registers for Time-to-Digital convert chip

    Re: An array of registers Thanks Kevin. You understood my problem perfectly. The registers are on the TDC chip and it is the goal of the FPGA to have some predefined values which are then subsequently written to the TDC registers. For this reason (among others), I wrote the read/write controller.
  4. I

    An array of registers for Time-to-Digital convert chip

    Re: An array of registers Is the above code synthesizable? Also, I believe the initialize only works in simulation mode not in actual FPGA logic. Is this correct?
  5. I

    An array of registers for Time-to-Digital convert chip

    Hi, In a controller I am designing for a Time-to-Digital convert chip, it asks that before being able to read time samples back from the chip, a bunch of registers are loaded with specific values. I wrote the read/write controller for the chip and now I am writing a FSM to go into a Configure...
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