Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
At first,thank you very much. But i think error at less than 1% need GBW=100MHz because [loop_gain /(loop_gain +1)]=0.99.
loop_gain=100 and -3dB frequency is 1MHz,so GBW =100MHz
And what i want is 0.1% ,so GBW=1GHz.
I want to ask a question about GBW and BW.
I have a questions: If feedback coefficient β is 1 (buffer) for cases and input signal frequency for 1MHz ( ignored SR of problem), hope the precision of output signal is high (1 per thousand). So we should design loop gain as 1000 around at 1MHz for...
Thank you.So you mean that I shouldn't concern DC term ,and I should focus on Tran term? But now tran voltage is not what I want because some DC current of VCCS flow into R1 then the current flowed R2 is smaller than I wish so that (i2*R2+i1*R1) is smaller than regulator.Shoud I change the W/L...
Hi!Did anyone done LDO VCCS compensation? I did a LDO VCCS compensation, through the voltage-controlled current source to introduce a zero point to elimanate the second main pole. but I have a question, is this VCCS output between access R1,R2 will affect the static working point? as shown in...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.