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Recent content by ibtesam90

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    TetraMax: Generating valid output for custom filled Patterns

    Hi All, I am new to Synopsys tools, I have generated X-filled patterns using Tetramax and then I have done some reordering of the scan cells based on those patterns. I have inserted scan chains according to the reordering that I found and I have filled those patterns with either 1 or 0 using...
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    MISR polynomial selection criteria?

    Hi everyone, I am trying to understand how to select the multiple input signature register (MISR) polynomial? I am trying to use 16 bit and 24 bit registers and convert those into a MISR in one mode and normal parallel data loading registers in other mode. I have looked into Built-In Logic...
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    Synopsys TetraMax ATPG B16-1 and B12-1 Error

    Dear All, I am trying to generate test patterns for a test bench circuit "wb_conmax" by opencores. I have successfully generated the gate-level netlist. And I had successfully inserted the scan chain. However, I am unable to generate test patterns. It gives following error The script I am using...
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    Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Thanks to all who guided me. I am able to resolve the issue and get the right simulation results. The workaround, which resolved the issue for me, is to manually define the VSS and VDD terminal in starrc Design. For the people who are like me, a novice and having this problem, you can open the...
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    Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    I checked *|Net section and i found the following code: " *|NET VIN 0.000819726PF *|I (MM0:GATE MM0 GATE I 5e-17 -3.79 4.29) // $llx=-3.79 $lly=4.29 $urx=-3.79 $ury=4.29 $lvl=30 *|I (MM1:GATE MM1 GATE I 2.5e-17 -3.79 2.16) // $llx=-3.79 $lly=2.16 $urx=-3.79 $ury=2.16 $lvl=29 *|P (VIN B 0 -4.105...
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    Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Here is the result of that SPF file. It contains the VDD and VSS. "* *|DSPF 1.3 *|DESIGN inverter *|DATE "Tue Oct 22 23:50:15 2019" *|VENDOR "Synopsys" *|PROGRAM "StarRC" *|VERSION "L-2016.06-SP3" *|DIVIDER | *|DELIMITER : **FORMAT SPF * ** COMMENTS ** OPERATING_TEMPERATURE 25 **...
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    Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    I am a novice in this. by the extraction script you are referring to .tcl file and then running it on console. I am using GUI following the guide from following link: https://github.com/sheldonucr/ucr-eecs168-lab/tree/master/lab1 I have followed each and every step as it is described in it.
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    Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    I am using Synopsys Custom Designer. I tried to search the using "DSPF" in my working directory. only files that comes up with this search are the OA2DSFP.tech files in Lstarrc.lpe folders and they contain many arguments and one on of them is "-ground_node_name VSS", however they do not contain...
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    Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    yes, I did put text labels using "M1PIN". All the four labels i.e., VDD, VSS, INV_IN and INV_OUT. The Layout VS schematics is passed without any errors.
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    Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    I am designing a very basic gate (inverter) in custom designer using SAED PDK90nm. I am able to create the schematics and layouts and generate Parasitics. When I run the simulation on testbench circuit (using schematic only) it works fine, however, when I run the same testbench with parasitics...
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    Can't Read SAED32nm libraries for design compiler

    Thanks for the suggestion. It worked but even after reading the libraries Compiler is unable to link the design. I am using a benchmark circuit s298 form ISCAS89 benchmark circuit. The following errors are being shown: Information: Building the design 'NAND3X1'. (HDL-193) Warning: Cannot find...
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    Can't Read SAED32nm libraries for design compiler

    I have attached the screenshot after the said changes. I hope I got what you wanted to say. Still getting the same error. Pardon my ignorance, I am new to this thing.
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    Can't Read SAED32nm libraries for design compiler

    Hello everyone! I am new to Synopsys tools and i am having trouble using the 32nm libraries provided by Synopsys. I am trying to set the link libraries through following command: set link_library {"../../../../../general_libraries/Libraries/SAED32_EDK/lib/stdcell_rvt/saed32rvt_ss0p95v125c.db"...
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