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One thing in Verilog always gives me fits:
assign data_out =
((output_select == 3'h01) * {2'b0, saved_rx_data[12:7]})
+ ((output_select == 3'h02) * {1'b0, saved_rx_data[6:0]})
+ ((output_select == 3'h03) * 8'h00);
This statement only produces 1 bit because of the logical equal-to sign...
Here's a little feature with Quartus II that's giving me fits.
I'm trying to create a PLD project using Verilog in Quartus, but I have a bug in my code somewhere. Because of the bug, though, Quartus is deciding to optimize my design. A large portion of my design is no longer being synthesized...
How many of you use the auto-routing functions in your PCB layout packages?
I'm torn between using it or doing everything by hand.
I typically work with *very* low volume boards (3-4 max).
On on hand, I save a day of labor by going the auto-route route. On the other hand, manual labor looks...
Re: How to check Protel DXP PCB connections against schemati
1. Did you import your netlist into Protel?
2. If so, did you run a design rule check?
A DRC (found under Tools / Design Rule Check... I think) will go through and validate all your design rules AND point out if you have unconnected...
sscanf would work...
It's in stdio.h
<# of items formatted> = sscanf(<source string>, <format string>, <target 1>, <target 2>, ...);
In your case, I think the target string is: "%s:\"%s\""
I could be wrong, though...
- Nobody
...
I'm the only one who picked #4 (Some other languages/tools.)
I have to program in AHDL (Altera HDL) due to my company's continuing adoption of the language.
It's an HDL without procedural blocks! Everything is concurrent, making simple counters more complex than they should be.
If I had...
They sound nice in theory...
"Hey, I can call my symbol \q' or \~q instead of something silly like qbar."
...but in practice, they're a complete nightmare.
Why? It's so easy to omit the trailing space that tells the compiler where the escaped identifier ends. If you're adding things to a...
How exactly do you come up with the total static error for an ADC?
I know you have factors like the gain, offset, INL, and DNL that factor into the static ADC error. But... how would you go about putting them together and obtaining an overall error number?
I want to be able to say, "this ADC...
I don't know if this helps, but Protel lets you run a signal integrity check after you have your board laid out...
- Nobody
- Stays out of RF land as much as possible!
I've seen Orcad PSpice used for schematic capture more than simulation. I don't personally use it because I hate how clunky it feels in wiring up circuits.
(This was 2 years ago - has anything changed?)
Protel can be used for capture and simulation, too, but I use it exclusively for its PCB...
I don't know exactly what's the case in VHDL, but in Verilog and AHDL (Altera HDL), all arith operators work.
That's because you can treat a multi-bit structure as either an array of bits or as a whole integer. In Verilog, 8'd123 + 8'd123 = 8'd246, and that's a perfectly synthesizable...
My advice would be to get a copy of Electronics Workbench / Multisim.
**broken link removed**
You draw your circuit up, connect a multimeter or oscilloscope to the circuit, and turn it on.
- Nobody
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