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Recent content by ian77316

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    vlsi mini projects based on fpga design using hdl verilog

    Re: vlsi mini projects based on fpga design using hdl verilo Hi sudhirkv, I first want to be properly grateful to u.I know this should work if all the timings are OK. and I use modelsim and LA to find the error,but I cannot find any error. however, when I take it to another...
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    vlsi mini projects based on fpga design using hdl verilog

    Re: vlsi mini projects based on fpga design using hdl verilo hi sudhirkv, I have done as you say and also seen the datasheet but the result is wrong. I still can not find why column address does not change. What are the reasons can cause this...
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    vlsi mini projects based on fpga design using hdl verilog

    Re: SDRAM controller Hi leonqin, thanks for your suggestion but my boss asked me use Xilinx. Hi mytechface, do you mean that CAS should be "low" when read and write? And the other time it should be...
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    vlsi mini projects based on fpga design using hdl verilog

    Re: SDRAM controller My SDRAM controller is set at 30 MHz and latency=1 clock. I use the verilog. ------------------------------------------------------------------------ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: //...
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    vlsi mini projects based on fpga design using hdl verilog

    SDRAM controller My boss gave me a job is to design a SDRAM controller. The SDRAM is produced by the Hitachi and the model is " hm5216165". I already design it according to the datasheet . However, I encountered a big problem. I can use the mode of "single write/single read",but when I ues...
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