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Firstly I use the ideal inductor and capacitor to design
Then I instead of real passive component
but the performance change very much
how to use real passive component to simulate CMOS RFIC
I use ADS with TSMC model
The Q of inductor is very low which change with freq. and geometry
I try to...
I am confused about gm=1/50
when I tune the transistor width size and bias to vary gm
I found when gm=0.02 but not to match 50 Ohm Zin real part is not 50
I chose Detailed in s-parameter simulation to watch Gm
what's wrong with my operation?
I am so confused about a source degeneration inductor
what element should I put to prove the funtion in ADS schematics?
give me the right schematics and the right procedure
thanks
Wopt=1/3wLCoxRs
the unit is so weird Wopt um Cox mF/m^2
may u give the CMOS gate width for 0.18 um TSMC at 2.4GHz?
I have the big trouble in designing the LNA
I use NFmin VS bias to find minimum NFmin
and then I plot ga and noise circle
I find their vswr r very high so it make very mismatch
S11 is very very bad
how to solve?
The paper say that CMOS biased in weak or moderate inverse region is suitable
for low power application.
which curve should I plot to find the region?
May u give a ADS example?
Re: Matching issue
only use source degenerater and gate inductor to match 50
center frequency is 2.4 GHz
and in your example the inductor value is huge
no process supply this value
I use ADS to simulat the NFmin vs bias
I am so stupid. I should plot NFmin vd Vbias and I-V curve
but i find someone can only plot NFmin vd Ibias
if someone have an idea, may u give me the ADS example
After i determine the bias and width, i use inductor etc. to match
but the nfmin is...
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