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Recent content by iammituraj

  1. I

    Integrated Clock Gating Cell - Timing Constraints

    Thanks for the response. What about generated clock? Should I create it at ICG output with same period as clk?
  2. I

    Integrated Clock Gating Cell - Timing Constraints

    I have a negative latch based IGC like this in clock path which takes care of glitch on switching gate. 'gate' is coming from another clock domain sysclk. All clocks (clk, sysclk) are defined in SDC. Do I have to add any additional constraints here like clock gating check? I have a feeling...
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