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I changed the design with this, but the dac still not working :
CLR <= '1';
Sclk <= Sclk_temp;
if rising_edge(Sclk_temp) then
if i>=0 then
LDAC <= '1';
Sync <= '0';
SDin <= data_to_send(i);
end if;
i:=i-1;
if i<-1 then
LDAC <= '0';
Sync <= '1';
if i<-2 then...
Hi,
data_to_send is constant in order to debug this driver : it's for setting the dac output other than 0V.
Sclk_temp is syncronised with Clk using the generation_horloge process. In simulation and in reality it seems ok but how can i improve it ?
Hi,
I'm working with a Spartan 6 and I'd like to drive an AD5781. I've written a VHDL SPI-like driver but the DAC remain at 0V .... so there is a problem with my vhdl ...
Here my code, if you can take a look at it and tell me what is wrong - Thanks in advance :
library IEEE;
use...
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