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Thanks guys to all the replies. I did manage to get it working, that is that the code does work I ran the code through a Altera software pack rather than the xilinx 10.1 package I was using, the code simulates perfectly in it.
I'd like to just say thanks to everyone for helping.
Also vipinlal...
I tried to fix this by creating more output pins as so:
entity MultiplexerX6 is
Port ( DataStreams : in std_logic_vector(191 downto 0);
SelectLine : in std_logic_vector(11 downto 0);
AOut: out std_logic_vector(7 downto 0);
BOut: out std_logic_vector(7 downto 0);
COut: out...
Your right! I've made some changes to the code but it looks like it not working again.
Code:
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entity MultiplexerX6 is
Port ( DataStreams : in std_logic_vector(191 downto 0);
SelectLine : in std_logic_vector(11 downto 0)...
I see what you mean, but there are 8bit outputs for each ABCDEF (OUTPUT's). You see I'm trying to generate 6 Multiplexers that take 32bits as an input and release a 8bit output. By assigning ABCDEF(0) <= OutA_temp(0); means only 1 value in the vector is being allowed to output does it not...
Having some real problems with some port mapping I know its probably something really easy, But I'm new to VHDL so I can't figure it out, would really appreciate the help.
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Code:
entity MultiplexerX6 is
Port ( DataStreams : in...
I'm new to VHDL so i'm still trying to get to know the basics. What I'm having problems with is a 8-bit DFF(Flip Flop) what i'm trying to do is recreate this program 6 times so that when the 8-bits go in it hold them till a total of 32-bits are held then release to a single output. I keep...
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