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Hi All,
If I am going to design an op amp, with a tiny current to get low power consumption design, the calculated w/l would be very small, can I use like 1um/40um for w/l? will there be some drawbacks?
I saw some threads that is saying that we can use a large L for designing large resistor...
Hi beeflobill,
Thank you sooo much for your reply, finally I fixed this problem, I found a way to run LVS without translate the .v to .cdl since Assura could read .v directly, just need to change some parts in the digital part's netlist, and the standard cell cdl file, also in the cdl file of...
Hi,
I am designing a mixed signal circuit, while for the digital part I could run LVS directly using .v file from encounter with the standard cell cdl file, but for a mixed signal circuit, and I don't have the nettran from synopsys and v2lvs from calibre, we have only assura to run everything...
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