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Recent content by hustyw

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    IBM ASIC design center recruitment (SH China)

    ibm asic design china ================Who we are================= We, the IBM Chip Design (China) team are the IBM local IC design center in Chi na of IBM STG MD(Microelectronic Division), which provide IC design services to the clients all over the world and support IBM internal chip and s...
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    Who has vhdl 2002 specification document?

    I need it . Thank you very much!
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    can any body explain me wht is SDF Annotation

    As it's said before,sdf is a kind of timing file . It can be generated from simulation model when we do pre-sim which not care for net delay. In post sim,we can extract RC delay from net parasited parameters. Then,we can give both net and gate delay for simulation, it is called back-annotation...
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    How can I get op-amp model in Hspice?

    I wanna design a circuit containing comparator and integrator. I'm a freshout in hspice ,how can i design a simple op-amp or download one?
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    NAND or NOR is faster

    another question: nand and nor , which one has less area?
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    How can real time clock keep track of clock after power down?

    who knows how can real time clock keep track of clock after power down ,what's the relation between RTC and clock unit?
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    Help:about perl script

    I have done it within a week,it really a tough job. It takes a lot of time to parse the module hierachy and macro , and key words etraction should be careful to avoid duplicate and lost of each submodule linked to top. Added after 5 minutes: By the way , r there any forums or websites that...
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    What's the meaning of LPC/HPC(Low/Hi Pin Count) ?

    need explanation ,thx!!:?:
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    anybody explain RTC for me?

    So,RTC is a peripheral module which can keep track of time even when power off. Am I right? Thank you very much!:D
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    anybody explain RTC for me?

    I'm a new comer here, don't understand what RTC for ?Thx a lot!
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    Compare latch based and register based design

    latch based design What differences they have? What factors determine certain kind of design?Such as area ,speed ,power, and so on. What else?
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    Help:about perl script

    Hi,all: -------------------------------------------------------------------------------- I wanna write a perl script to control and run a design flow . I'd like my script can find and print each level depth module(submodule) of netlist after RTL synthesis. Another words:When given a...
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    Help me write Perl script to control and run a design flow

    Re: Help:about perl script I wanna write a perl script to control and run a design flow . I'd like my script can find and print each level depth module(submodule) of netlist after RTL synthesis. Another words:When given a netlist, the chosen depth of submodule and nodes can be listed out just...
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