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Recent content by huster

  1. H

    Output Delay Problem For 32 bit output (+ 50 points for sol)

    Clock all output signals, Using the registers in IOBs
  2. H

    Question about quadrature sample

    In quadrature sample.ADC sample at T/4,T/2,/3T/4,T。 I want to know how can we control the ADC sample time at T/4,T/2,/3T/4,T exactly? Thanks!
  3. H

    Can I increase the size of RAM, as I need some BRAM?

    RAM Utilization You can modify some Block RAM to Distributed RAM in Core Generator.
  4. H

    How to map hexline in IOB of Xilinx FPGA

    What is hexline?
  5. H

    [FPGA] Clk Multiplexing

    you can use bufgmux to implement the clock mux function if you use Xilinx' FPGA
  6. H

    What simulator are used for Verilog programming?

    Verilog Help Modelsim
  7. H

    Which FPGA is better: XILINX or ALTERA?

    Xilinx or @ltera It depends your requirement. I prefer Xilinx. It is my personal opinion.
  8. H

    Seeking VHDL Good & cheap FPGA designer.

    You can contact with me:)
  9. H

    Why there are different results in Synplify and Leonardo?

    Synplify vs leonardo? The market is always right.You can see the market share.
  10. H

    Suggest me a low cost FPGA chip for beginners

    Low cost FPGA Chips ? If you prefer xilinx,SpartanIII may be the best choice.
  11. H

    What is better for FPGA manufacturer, Xilinx or Altera?

    Re: Xilinx or @ltera? qu@rtus has very powerful synthesizer and simulator. R U JOKING?Do U know the mean of powerful?
  12. H

    comparing synthesis tools.

    Sometimes Xst may be better I think.
  13. H

    implementing a delay in FPGA

    Use a high frequency clock is the only way.
  14. H

    Can I set different I/O standards in one bank? (Stratix II)

    Place and Route Problem I think you can not
  15. H

    Why do FF and latch require a setup time?

    SET UP TIME Because all semiconductor devices have delay.
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