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Recent content by husain154

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    what is the core limted design and pad limited design?

    pad limited core limited If the size of the core is a factor responsible for determining the size of the whole chip, then we say that our design is core limited. But if the core is too small, and the number of pads are too much to the extent that the size of the chip is determined by the space...
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    DRC clean with encounter, but DRC errors with calibre

    SoCE gives no DRC errors, but Calibre gives many. The DRC errors mostly comprise of 1. The density and the Poly area coverage errors. Also, layer M1, M2 .. M5 area coverage must be >X% and <Y%. 2. M2 with >= X um wide and <= Y um long must have hole (This error is with the segments...
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    LVS without GDS of standard cells

    Great; That works. Thankx everyone. Just for information for others:- I didn't had "SVRF commands" tick " option. I just created a text file and wrote the command "LVX BOX cellName1 cellName2" in the file. I included this file, and that worked.
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    LVS without GDS of standard cells

    Okay. Can you please precise, where to enter the command LVS BOX <cellname>? With "Calibre LVS", i have got a GUI interface. I am unable to determine the exact place where this command can be entered. -Husain Thankx chinnisunny, but i havn't got calibre manual either.
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    LVS without GDS of standard cells

    lvs box Hello, I have developed my layout (GDSII) using two types of "standard cells". A. The standard cells developed in our lab, (Standard cells 'A') B. The commercial standard cells of a company. (Standard cells 'B') I have got all the details (layout, abstract etc) of 'A'; but for 'B'...

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