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Hi slutarius:
3ks for you reply. I don't understand why one clock cycle is added in the Data required Time (DRT) calculation in the second example:
Data required Time (DRT) = one clock cycle – clock uncertainty – output external delay + max_delay requirement value
which is different...
In PrimeTime® Fundamentals User Guide Version D-2010.06, June 2010, P6-3, a report_timing result is shown below:
pt_shell> report_timing
****************************************
Report : timing
Design : FP_SHR
****************************************
Operating Conditions:
Wire Loading Model...
Hi all:
I was dumping several fsdb waveforms using verdi at specified time, such as 1042800ns、2085600ns、2607000ns、4171200ns...
At each sampling time, 200ns fsdb waveform is recorded using $fsdbSwitchfile、$fsdbDumpon and $fsdbDumpon with name dump_0.fsdb、dump_1.fsdb、dump_2.fsdb...
Hi shobhit:
Can I understand your explanation as follows:
1) SETUP analysis
Both data path and clock path can have a max delay(MAX_DELAY), but for correct samping reasons, data path must come earlier at least Tsetup time than clock path.
2) HOLD analysis
Both data path and clock path...
Hi all:
I saw the following descriptions for Setting Maximum and Minimum Path Delays:
pt_shell> set_max_delay 12 \
-from [get_cells REGA] -to [get_cells REGB]
With this timing exception, PrimeTime ignores the clock relationships. A path delay between
these registers that exceeds 12 time...
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