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Recent content by hugo92

  1. hugo92

    vhdl signal generator

    it's a part of question. i think the requirement that go changes from 0 to 1 two times consequently is impossible.
  2. hugo92

    vhdl signal generator

    Hi my dear friends I'm working on my home work and i can't understand the question. the problem is here: " a. When GO changes from ‘0’ to ‘1’ two times consequently, the output UP must go to ‘1’, but T = 10 ms later. b. When GO changes from ‘0’ to ‘1’ two times but not consequently, the...
  3. hugo92

    Flip flop contamination delay tccq with hspice

    Hi , I'm trying to calculate a TSPC flipflop charecteristics. The problem is how i can calculate tccq in my program which is like this: I think there is not a contamination delay from clock to Q , it's just a propagation delay from clock to Q.
  4. hugo92

    A TSPC DFF sizing & simulation

    The problem solved with assigning Wn > Wp in all 3 branches & m6 , m7 = m4 , m5
  5. hugo92

    A TSPC DFF sizing & simulation

    Hi , thanks it deleted two warnings but didn't improve simulation result
  6. hugo92

    A TSPC DFF sizing & simulation

    Hi , As a project i'm triyng to simulate a TSPC Flip flop that works correct. I don't know where s the problem that my program works incorrect. This is the Pos edge TSPC flip flop: This is sizing I choosed: And this is my Hspice simulation waves: it's obvious that flip flop isn't working...

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