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This old thread is the first hit on Google when searching for an LTSpice model for the IRL510.
In case anyone else is searching, I just wanted to report that the model posted in that thread does not appear to be compatible with LTSpice. In particular, the LEVEL=17 parameter for the NMOS model...
I'm not aware of any general rule of thumb. More practically, it comes down to tuning it for the circuit and design constraints at hand.
Of course, the most efficient dead time is zero, but the closer you get to zero the greater the likelihood of shoot-through. Typically shoot-through is...
Wow, great story. Would love to see some photos of the B switch repair but suspect it would be hard to capture.
Can't help but feel there's a common cause to these multiple failures. I wonder if the issues with the power inverter have produced voltage stress on downstream components. Perhaps...
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