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Hi all,
I have designed a 10-bit SAR ADC. Now I need to measure the PSRR performance of the ADC.
I read some articles. It says I will need to inject a 100mV sine wave to the power supply and ground the input. Capture the output code and process it with FFT. I have done so and get a spur of...
Hi All,
I am trying to build a long-distance passive RFID tag working at 900MHz range (something very similar to the WISP developed by Washington University). Anyone has any hands on experience?
In addition, is it possible to run any simulation on the discrete components before I purchase the...
Hey guys...
I have obtained a series of measured digital data from logic analyzer.
May I know if anyone of you has the matlab script, or know how to get the SNR of my ADC using Matlab?
Thanks!
HI all,
I have just done a single MOM capacitor extraction. I found that the top plate of the MOM capacitor has quite a huge parasitic capacitance (about 5% of its own capacitance, and bottom plate is even worse). Therefore, I am wondering if MOM capacitors can be used to form the capacitive...
Hi all,
Does anyone of you have any example of a common centroid layout for the capacitor array used in a 9-bit SAR ADC?
The binary weighted array is listed as below:
16C, 8C, 4C, 2C, 1C - 1C(Split Capacitor) - 8C, 4C, 2C, 1C, 1C
Hi dinesh,
Thanks for the help!
I try to do an auto routing for a simple inverter. First, I generate the 2 transistors (1 PMOS and 1 NMOS) using "Gen from Source", then I include the predefined rule file in the "Use Rules File" column.
A "Virtuoso Chip Assembly Router" window pop-up, with...
Hi all, does anyone know how to use the "Routing" function provided in the Virtuoso XL Layout Editor?
I have a custom design digital block, however, the parasitic has given me some headache, therefore, would like to try out the auto route function, so that I can keep trying different routing in...
Thanks for the solution!
In addition, may I know the ideal DAC should have an ideal transformation characteristic (eg. 1 V using 10-bit, so each LSB will be 1/1024), or same as the ideal transformation characteristic given by the ADC (assume there's a known gain or offset error in the ADC)?
I am currently designing a 10-bit Charge-Redistribution SAR ADC. I will be using MOM capacitors to form the Capacitive DAC since MOM offer smaller capacitance and hence, smaller power consumption.
However, does any one know which configuration of MOM capacitor is better for the design? For...
Hey all,
I am using cadence-icfb to simulate my 10-bit SAR ADC.
I have noticed someone manage to simulate the ENOB, does anyone know how to do it in cadence?
Thanks!
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