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astro create placement
I'm trying to lay out a design with two large modules connected by some simple glue logic. I want the modules to be laid out physically as two separate bodies on the chip. I know the placed-and-routed area of each individual module, and I'm using that for two plan groups...
Re: Missing .sdb file
.sdb does appear to be just a symbol library for graphical schematics, and is definitely not required for my design. I would like to follow up with trying to generate the new .sdb file for the 45-nm library, but I'm currently busy with higher priorities. If someone else is...
Solved. My problem seemed to be a combination of script order (as you suggested) and unique names. For future reference:
I was using "set_dont_touch" too early, but even after moving it later in the script, I still ran into a problem during floorplanning involving unique names. Without the...
Re: Missing .sdb file
Here is a part of the .tcl script we use for our 90-nm flow:
...
set LIB_ARTISAN "tcbn90ghptc.db tcbn90ghpwc.db"
set LIB_PDB "tcbn90ghp_9lmT2.pdb"
set symbol_library {"tsmc90ghp.sdb"}
set target_library $LIB_ARTISAN
set physical_library $LIB_PDB
set link_library...
My group is trying to make the move from 90 to 45 nm. I downloaded the 45-nm library files from Synopsys SolvNet, but I'm missing a .sdb file. I believe this is a Synopsys-specific symbol library, is that correct? Is there a way to generate this file from other .db files?
set_dont_touch design compiler
Thanks for your quick reply. I have another question. When I use set_dont_touch, I get some warnings like this:
Warning: Unable to resolve reference 'shiftReg' in 'foo'. (LINK-5)
Warning: Unable to resolve reference 'adder' in 'foo'. (LINK-5)
...
Warning: Design...
set_dont_touch on cell
I used Module Compiler to create some fast adders. How can I tell Design Compiler not to change them?
Say I have two instances of this module, adderInst1 and adderInst2. I've tried using "set_dont_touch adderInst1" which works for just one instance, but how do I use * to...
post synthesis gate level simulation
Short version:
How to configure VCS to understand multiple clocks for a gate-level simulation after clock tree synthesis and routing?
Long version, with details:
Are there any special tricks/command-line options necessary for running a post-synthesis...
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