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Thanks. This is what I was looking for. I just needed one more advice. Do you know any tool where I can sketch the schematics. I need a tool where I can easily draw the MOS transistor based schematic, label the node voltage and branch currents, write explanation about the circuit behavior etc...
Hi,
I am planning to start a blog on analog circuits and am looking for a model card to demonstrate simulation examples. Can anyone point me to any freely available model card which I can use and even re-distribute on my blog site? It need not be a high end node; just something good enough to...
OK. Pls. tell me any books which provide info. on 50nm/ 32nm leakage current. I will get it. (Books anyways give better explanations than papers)
Its work related; other than that there are papers (easily available) on the internet (on leakage current mechanisms) for the previous generation IC...
OK. I wanted to know the leakage current mechanisms for nano meter scale processes - like 50 nm, 32 nm and so on. I dont have any pdks with me. Do you have / can you point me towards relevant documentation? is there any benchmark review paper on it that you may be aware of?
Thanks and Regards...
Hi,
What are the leakage currents in nano-meter range CMOS processes used nowadays. Can anyone point me to relevant documentation pls?
Thanks and Regards,
Hobbyiclearner
Thanks. This would help. I suppose the operating voltage will be 1.8 v. Also, in the given link, there is a process characterization kit. How to use it (though I can get the main values directly from the model deck - I am just curious to know how to use the characterization kit). It seems to be...
I observed one funny thing in the model card. The 'tpb' parameter has been repeated twice in the pmos model parameters list. Not so for the case of nmos parameter list. Attaching the model card here for your reference. Do you think the model card is reliable? though i wont be fabricating any...
Thanks. As of present, I will just use the APDK model card with LTSpice. BTW do you happen to know the supply voltage of this technology. I was unable to find it in the associated pdf. Attaching it here for your ready reference.
Regards,
Hobbyiclearner.
I am planning on LTSpice (could you suggest a free online/offline simulator also?) . Its Ok if I have to increase the value of L. I just need a suitable tech node and corresponding model files for running general analog simulations. Thanks for taking interest in my query.
Arvind Gupta.
Thanks for your reply. Can you suggest a suitable technology node as well ? (350 nm/ 180 nm etc)? Also, could I request you to point me towards a suitable level 3 model file (typical) which I can use in this context. There are a lot of level 3 MOS model files on the net creating confusion for...
Hi,
I have to conduct Analog CMOS based training to under graduate level learners. The training will include simulating MOS based simulation of one transistor & multi transistor circuits up to 2 stage op amps. In this connection, I wanted to know which level of MOS transistor model parameters...
Thanks. I had 2 final questions pls.
** What is the advantage of using gm/Id designing technique over the conventional technique?
** Is there any name for the conventional designing technique? I am assuming that this newer technique is referred to as 'gm/Id technique'.
Regards,
Hobbyiclearner
Thanks. Pls. confirm if you were talking of this book: 'Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables'
Regards,
Hobbyiclearner
Thanks. I got a copy elsewhere. I just wanted to know two more things.
#This book written 20 years back would hopefully cover the details of CMOS Op Amp design of that era. Do you by chance know of any book which deals with the topic focusing on modern era CMOS technology in particular. At...
Hi,
I am looking for an old book (about 20 years). Will someone have a copy of 'Introduction to CMOS OP-AMPs and Comparators' by Roubik Gregorian. I wanted to have a look at it first.
Thanks,
Hobbyiclearner
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