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why my op amp oscillate?
For the plot I have given, the phase is not right.
I changed the structure of the class-AB output stage, and modified the compensation capacitor.
Now, it's ok.
Re: why my op amp oscillate?
I don't know how to display the pictures directly, so I have to upload the files.
I modified the circuit after I obtain this result, the result seems better, but the problem also exists.
Re: why my op amp oscillate?
the phase margin increases at 10MHz, reaches 60 degree at 40MHz, and then fall down.
I add a capacitor between the input and output of the second stage, but it doesn't work.
why my op amp oscillate?
Hi all,
I designed a folded cascode op amp with a class-AB output stage to drive a large capacitor. When I configure it as a buffer, it oscillates.
I did the .pz analysis, and find out that the frist pole is +16.3369MHz.
What should I do?
Thank you for you help!
Hi all,
I defined an ideal op-amp in hspice like this:
Eop out 0 OPAMP in 0 MAX=+5 MIN=0 4.0
The input is a pulse from 0 to 1.25v.
If there is no "OPAMP" in this syntax, the result is right.
If there is, the output swing between ±300v.
What should I do?
Thanks.
question about Hspice
hi all,
when I check the phase margin after ac analysis of amp, if the pm below -180 degree, it jumped to +180, how can I make it shown from 0 to -360 degree?
thanks.
design of analog coms integrated circuits ,by razavi
coms analog circuit design,by Philip.E.Allen
analysis and design of analog integrated circuits,by Gray&Meyer
thank you for your explain.
in my opinion, for a two stage op amp,the second stage is used to obtain large output swing.
so if I use a simple Gm amplifier, how could I obtain large output swing?
in my design, the input is a pulse from 0 to 1.25v, so I hope the output swing from 0 to 5v, if...
hi all
I want to design a CMOS buffer op amp. The Cl=90pF, input signal is a 30MHz pulse swing from 0v to 1.25v. The close loop gain is 4,Vdd is 12v.
Which structure is the best choice for my design?
thanks®ards
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