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Recent content by hiky

  1. H

    HELP: Timing about AHB hready

    slave input hready signal Sorry, phoenixfeng, i can't get your point, how the arbiter control the slave not coming into data phase? by generating 'hsel' signal or any other signal ? can you give me some more detail information? thanks a lot!! can the slave not have to see the hreadyg signal ?
  2. H

    HELP: Timing about AHB hready

    ahb slave hready signal thanks alam, but i have a question about slave change, how does the master know weather the slave is being to change or not? the slave is selected by hsel generated by address decoder, and the decoder is inside arbiter , the master does not see the select signal at all...
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    HELP: Timing about AHB hready

    ahb hready slave thanks for your reply, but i am readlly confused about How the current slave know the data transfer belong to the previous slave have been done if the slave don't care the global hready signal? can U tell me ?
  4. H

    HELP: Timing about AHB hready

    ahb timing In AHB, when the master change slaves, for example,from slave0 to slave1,the slave 1 must use the global ready at the transfer begining to check weather the last data form slave0 have transfered success. am i right? but the hreadg(global hready) is generated form all the hreay form...
  5. H

    Looking for AXI master/interconnect/slave code

    axi protocol is there anyone designing on the AXI protocol ? and who can share me with the AXI master/interconnet/slave code?
  6. H

    reconfigurable processor

    tencilica provides configurable processor ,and you can define your own instruction set, but i have no idea about reconfigurable processor,is it implemented by software? anyone can tell me more detail about the reconfigurable processor?
  7. H

    AMBA bus model - looking for it

    AMBA bus model needed if anyone can provide the cerilog code?
  8. H

    about the test environments of AMBA AXI and AHB

    dear, who can tell me where and how to get the test environments of AMBA AXI and AHB buses. is there have any open source code for testing the buses? Anyway, the avaluable test open source for the bridge from AXI to AHB will be the best! ! thanks!!
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