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I am totally confused now, can u please put your thoughts in a much simpler way ? I could not get even a single bit of what you explained. Sorry for the inconvenience.
i have already understood the term latch up, its cause, mechanism and remedies. But I got stuck at one point, I read in wikipedia that
It is possible to design chips to be resistant to latch-up by adding a layer of insulating oxide (called a trench) that surrounds both the NMOS and the PMOS...
For my design it is recommended to use polysilicon resistor and not an n well resistor, so then why it has three terminals? I think that as we are designing an integrated monolithic design, so substrate is same and hence the third terminal is for the body or bulk of the resistor on which poly Si...
While designing layout of analog circuit, I came across a resistor with three terminals in the schematic. The third terminal was connected to the bulk or the substrate which was in turn biased (vdd or vss). Can anyone explain me why this resistor had three terminals, what is its advantage and...
Hi guys I am designing the layout of a a differential amplifier in cadence virtuoso layout xl and technology node is 40 nm. This reqyuires matching of two nmos devices. suppose i made an array of 4x4 to macth two nmos devices, then according to the rule of 40 nm global foundries, how many dummy...
Thank you for your suggestion dick_freebird, but my mentor under whom I am doing my project strictly warned me not to use rectangle but paths for routing while designing analog circuits and he even asked me to find the reason behind this as to why we cannot use rectangle to route the same ...
Suppose I am connecting VDD to source of a PMOS and for this purpose, the dimension of the required route is 2um x 0.2um. Now what is advisable - drawing this route using the rectangle (r button on keyboard) or use the path (p button on keyboard) for the same route and why? basically what is...
Difference between n well drawing and n well pin layers in cadence virtuoso layoutXL
I am drawing a layout of an inverter in cadence virtuoso layout XL. The problem is there are two layers visible in P MOS one is n well draw and other one is n well pin. and by default it (n well pin) is showing...
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