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hello there,
Chopper amplifiers are sometimes called chopper-stabilized amplifiers, what does 'stabilized' mean here, does it mean chopper amplifiers are always stable ? please help, thanks!
regards,
henry
hello there,
can anyone tell me the main difference between duplexer and circulator ? what is a typical duplexer made up of ? Someone told me that circulator is used in TDD system, can a circulator be used in a full duplex FDD system, and why not ? Any comment is welcome, thank you in...
Hello there,
please help me read the datasheet of a opamp buffer. Part of the datasheet is posted here. In the DG (differential gain) field, what does '' RL=150Ω to 0V '' mean ? why does volt appear in the unit of a resistor? AND what does DG=0.06% mean ? thank you for reply !
hello there,
why constant bandwidth across the gain range is required in VGA/PGA design, what if the bandwidths of different gain settings are different ? Is there a fundamental principle behind this, any comment is welcome.
question about PSS setup
hello there,
what does it mean when the number of harmonics is set to 0 in a PSS analysis, is it mean we can only see the dc component ? please help !
hi there,
I found that the SFDR of ADC is larger , if not always, than SNR in the datasheet of commercially available ADCs or from my simulations. Is there a definite relation between these two parameters of ADCs ? why is SFDR larger?
Any comment is welcome!
regards,
henry
hi there,
Does anyone know how to simulate the noise performance(such as input refered noise) of OPAMP using HSPICE, can you share some hspice cards for reference. Documentations or links are also appreciated. thank you all!
regards,
henry
hi there,
I performed a transient simulation in hspice (.tran 1n 10ns), and make the hspice save the output (.option post=1) for post-simulation, but I found the output data (.tr0) is huge (not 10 points for each variable but much more than 10). Hspice does not save 10 samples for each...
Dynamic comparator
hi there,
Does anyone know why is dynamic comparator (rather than preamp+latch) frequently used in pipeline ADC design? what is the advantage of it compared to other structures?
adc 1.5bit
Hi, there,
As is well known, the comparators in the sub-ADCs of a 1.5b/stage pipeline ADC can tolerate offset error as large as Vref/4, but why is it that ? can someone explain in more detail or post some links here, thanks!
Added after 16 minutes:
AND I also want to know...
number of comparators offset
hi there,
what does comparator offset effect on flah ADC ? how does it affect DNL and INL or other ADC characteristics, I just cannot figure out the picture. If you have any tutorial or links, please kindly post it here, thanks!
regards,
henry
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