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Recent content by heng155

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    Generating the bias voltage of an op-amp

    Bandgap Reference you can use a opamp as a voltage follower, and a DAC which tuning up the 1.4V and VDD
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    Ring Oscillator with Delay

    You can use a much small & slower Ring Oscillator to set the timng.
  3. H

    please help me on veriloga debugging

    please help me on veriloga debugging. I wrote my first verilog-a script for lfsr. But it doesn't work correctly. thanx!
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    Why minimum W/L of transistor is 3/2?

    model file is for your to simulate your circiut Technology file is the define of your process layers, for you to draw the layout Someone call drc lvs rce rule files Technology file, for you to verify your layout
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    Offset varation in different processes

    offset www.extra.research.philips.com/mscs/publications98/IEDM_match.pdf
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    Shanghai Design Center

    Fudan, Jiaotong, Dongnan(southeast)... as protose said Chengdu and Xi'an University of Electronic Science and Technology are good as well
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    How to deal with noise on mixed Signal IC design

    guard ring for sensitive analog part, seperate vcca & vccd, decoupling capacitences for vcca (especially sorround sensitive analog circiut), decoupling capacitences for very big inverters ,add decoupling caps on your unused space , shied your long wire dc bias with power supply wire
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    RCE by calibre, how to do post-simulation with spectre

    spectre post-simulation Hi, I used calibre to do RCE, and set the output ‘format’ to ‘spectre’, ‘use name form’ to ‘schematic’. Then calibre generated three files: just_for_test.pex.netlist just_for_test.pex.netlist.pex just_for_test.pex.netlist.JUST_FOR_TEST.pex. The...
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    How to improve the PSRR of a Bandgap?

    The PSRR of my Bandgap is poor. AC:It is about 60db at low frequency. When noise is higher than 10KHz, the PSRR value qiuckly rolls down. And it reaches 0 at about 40MHz. Transient: 30mV supply noise got 80mV output noise!!!:cry: My schm. is attached. And the Op-amp's Gain is 76dB and roll down...
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    bandgap & BJTs in TSMC18

    You're right. Thanks!
  11. H

    bandgap & BJTs in TSMC18

    I don't think so. In double well process. Pplus(in n-well)-Nwell-Psub is a vertical pnp, so it's collection must be connected to gnd. L-pnp can put in a single n-well. plus-nplus-plus is a lpnp. When we have triple-well, a p-well in the deep-nwell, we can use npn, either vnpn or lnpn. Thanks!
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    bandgap & BJTs in TSMC18

    Hi, I'm designing a Bandgap in TSMC18 process. Simulation shows "beta" of vpnp is quite small, about 2.5; "beta" of npn is about 23. It seems I must use npn instead of vpnp? Why "beta" of vpnp is so small?(I've heard that "beta" of vpnp is bigger than lpnp, which is no bigger than 5) Why so...
  13. H

    cadence corners tool and mento carlo analysis questions

    corners analysis cadence You're right. But what I really want to know is how to set these variables. Or can U give me some references? Thanks!
  14. H

    cadence corners tool and mento carlo analysis questions

    cadence corner analysis Hi all, corners analysis is not avilable in my system. when I run it, icfb complains"corners tool preload not done yet,..." & How to use the mento carlo analysis tool? Thanks in advance!
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    What is the best Antivirus software on the market?

    Best Antivirus kaspersky Macfee I think

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