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Hi,
I am somewhat confused about view name and view type in Cadence tool, I assume they are different, but I am not sure I understand the difference, for example, as shown below
if schematic and layout (and mixedConfig, logicConfig) are view names, what will Sch1, Sch2, and Lay1 and Lay2...
Hi,
How is the RF design flow and methodology different from other analog design flow? I know somewhere along the line, the EM simulation may be involved, but aside from that, what is the major difference from other analog designs, starting from schematic entry, circuit simulation...
Hi,
The height is fixed as others mentioned, however when determining the height, it has a lot to do with the routability, for example, should it be 9 tracks or 11 tracks, the cell lib developers usually have to run a lot of P&R (Place & Route) experiments to determin the optimal height...
matlab plot
Hi, Blackuni:
I went to the discussion link that you refer to, and there are further links, however it seems the link
is no longer existent, I wonder if you have the updated one.
Also, I wonder if the gm/Id methodology can be applied to bias circuit where small...
Re: design chart (gm/Id) on the wide swing current mirror ck
I think a much bigger issue with the gm/Id methodology, as some already pointed out in this forum, is that it wasn't able to predict gds, and Vds (not Vdsat) well. Take for example, the voltages at node 13 and node 12 are to bias the...
current mirror +ckt
The attached circuit is a bias circuit for a folded cascode CMOS Opamp, I was applying the gm/Id methodology and design charts to do the transistor sizing. The process technology is 0.18um and the supply voltages VDD=0.9v, VSS=-0.9V.
While M12 and M17 are alwasy in sat...
Generally speaking, SPICE is NOT a design tool but a verification tool, that verifies the circuit in the way you think it will work. With that said, the way to reduce or minimize the lengthy SPICE run is to do the hand calculation first, that is pretty much what most designers will do in their...
Hi, aba380:
As cmos_dude pointed out, do yourself a favor and try Laker if you are talking about Virtuoso replacement, but you are only looking for Tanner, MyCad, kind of tool, Zeni might be an option if it's indeed cheaper than Tanner.
gm id design
Hi,
I have read a few papers regarding the gm/id design methodology, but I don't seem to completely get the concept. Can anyone walk me through with the included example circuit?
Assuming I have already have the following charts
1. gm/id vs. inversion level
2. ID/(W/L) vs...
From what I read about gm/Id methodology, I thought we will chart all spec as a function of (gm/Id), which can be associated with Inversion Coeff. However, EE214 notes also chart fundamental "figure of merits" as a function of Vov (over drive voltage), which I thought we want to avoid doing so...
I am self learning the essence of the analog design. From a paper I am reading, it seems that even for a very typical folded cascode OP Amp, depending on the approach, they can have a very different transistor ratio (W/L) for the same transistor(table 5), and they still all meet the spec (table...
The attached graph is from W. Sansen book, page 189 and I am a bit confused, on one hand, the text in the book seems to suggest that the rule of thumb is that Cc should be smaller than CL, on the other hand, the gm chart seems to indicate that the optimum Cc is about 4x of CL, my question is...
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