Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have a doubt about the SystemVerilog code snippet.
sub_top #(
) inst_sub_top (
.count((VALUE[FACTOR-1:0] - {{(FACTOR-1){1'b0}},1'b1})),
.dummy()
);
where VALUE is a parameter defined as 4, while FACTOR is a local param which is a 2.
How to understand this line...
for example
DFF1X means initially at the 0th simulation time DFF holds a logic 1 value and as the simulation moves-on further then DFF storing dontcare X ?
am i right ?
Hello,
I am very new to formality and running a entire soc reference and its implementation for equivalence checking in formality tool.
i am getting this report
20 Failing compare points (20 matched, 0 unmatched)
0 Aborted compare points
88545 Unverified compare points...
Initially I found that the master (processor) not getting its requested RVALID ,RDATA, RLAST from the slave. I thought of problem with the slave which may be not responding.
But, After adding all the signals to the wave window then only i figured out that the RVALID , RLAST and RDATA nicely...
No. I think its deviated.
The processor(Master B) requesting a data from the slave(a memory buffer with axi slv interface logic) . the slave giving the data to the AXI3 slave port (i can see that data is presented back to interconnect slave port) . but on the other side (i mean at master...
Hi,
This is about the axi3 interconnect. Here , In my SoC there is a axi3 interconnect with two masters A and B. where A is a CDMA and B is a processor .
And only one axi slave is connected to this interconnect.
The issue is, when the master B requests a data from the slave. then there is...
with my novice knowlege . i explored all the options available in the sdk gui but unable to figure out how to instruct the IDE. i searched help-> help contents. but no help on this topic(or they may be using other sw terminology which i dont understand).
on googling, I found objcopy command...
In this case ".elf" is generated for a arc processor from a synopsys metaware IDE SDK tool.
I want to convert to .bin or particularly .hex file so that i can use it for a verilog memory initialization file ($readmemh) and do some simulations.
Thanks
the question posed to me is, how to fix setup violation ? my answer is to reduce the combinational path delay sitting in between Lflop and Cflop.
the next question is, how you do that ? my answer is, By registering the data available at certain point in the combinational logic.
the next...
the .rpt file that comes after the command "report timing -num_paths 3000 > timing.rpt" during synthesis. From the textbooks what i came to know is, net-to-net violations is addressed using "set_input_delay" constraint. Is that true ??
I am looking into STA theory. why you ignored IN-OUT path.?
In the attached picture , I am talking about path-no 4 .
And how to fix violations for the paths which is through a combinational logic like path no 4 ??
Hi,
1.)why INPUT-to-OUTPUT path in sta is considered as a combinational path (not as both comb and seq) even though u see one launching flop and capture flop in between these ports ??
2.)how this net-to-net setup/hold violations are fixed ??
Hello,
This question correctly relates to this thread, I believe
I am writing a driver c code for altera fpga modular scatter gather DMA. where i have to decide the number of descriptors (that contains read address, write address, length of transfer and control field) and then i have to pass...
Hello all,
please suggest me a reference design on stratix 10 board with a PCIe , enabled high performance burst interface (HPTXS) port of 256 bit width.
I searched on the net to have a clear understanding about this port, but not found anything. But, there are 2 paras of information...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
