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Re: op amp dc bias phase shift
Dear Walk4567,I got the same problem in my class AB opamp in GRACE 1.8/12V device process.I want to know: Have you sloved this problem or got some conclusion of this problem?
Thanks!
erikl wrote:
Yes,you are right. Because the MOM cap model is quite well.But still congratulate you achieve 12-bit resolution.By the way,what time we can share your experience from publication?
timof wrote:
what timof have mentioned above are real problems when used the interconnection...
Hi, timof
(~0.1%) is the relative precision(for example:C2/C1) or absolute precision for a MOM capacitor?
Does this tool(F3D) use table-based method to caculate parasitic capacitors?
Hi,erikl
Thanks for your reminding.For a 12-bit SAR, the tool is not enough accuracy.
I think it's only can...
Hi,timof
"Accurate extraction of parasitic capacitance
helps ensure linearity of SAR ADCs
Maxim Ershov
Silicon Frontline Technology, Millich Dr., Suite 206, Campbell, CA 95008, USA
Phone: 1-408-963-6916, Fax: 1-408-963-6906, E-mail: maxim@siliconfrontline.com"
you means you can provide...
why the minimal channel length is 240nm in .25u technology of NCSU_CDK?
Hi guys:
I have drawn an op-amp circuit in the schematic of cadence with the tsmc_03d-technology in NCSU_CDK_1.5.1.Its .tf file is as follows:
"TSMC 0.25u
controls(
techParams(
( lambda 0.12 )...
hspice for linux
thank you every guy,the problem have been solved for you help!
By the way,why hspice can generate the data files in windows without the ".option post" statement?
hspice not generating .sw
I installed hspice_2005_03 in redhat9.0 .The hspice can run. But it can not generate the files,such as *.sw*,*.tr*,*.ac*. So i can not observe the waves with cscope.
there is the *.lis file:
Using: /home/cs/synopsys/hspice/linux/hspice
Incorrectly built binary which...
To mdcui:
Thanks for your help!Is this optimizaton way for digital circuits?
Added after 22 minutes:
To mdcui:
By the way,I don't know its' optimizational goal.Can you explain the goal of this optimization for me?
Thanks!
tot. iter in lis file in hspice
To pit1000:
Thanks for your help!As you said,each following .alter uses input netlist from previous, instead of from head.I also find similar statements in the hspice manual.But how to prevent the preview .alter statement change the netlist?Maybe it...
differtial circuit
yeah
But if citrcuit is differential input and single ended output and it's load resistance not current mirror,it will not restrain the common-mode signal.
hspice alter site:edaboard.com
To pit1000:
"Try to put .probe statement before the last .alter statement. "
I have tried what you said,but it still have the problem.Nothing changed.
Seem that the dc analysis implements twice.
Is the ".connect p n" statement affect the simulation results...
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