Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I need help in completing my semester project on verilog. I have made the code and it is compiling well but when I try to simulate, I get dozens of errors. I will greatly appreciate if someone can guide me with this coz I need to transfer the code on Spartan-3 fpga very soon. Here is the...
verilog 2s complement
Can you please code the following in verilog:
A low level module in my project has an input bus of 11-bit and an out bus of 22-bit. Firstly, I need to get the 2's complement of the input and then multiply it with the original input.
thx
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
