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Recent content by hassanzia

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    [SOLVED] Ideal value of Form Factor for a rectifier

    Thank you, I guess I was indeed confused about the concept of an ideal value. Now its cleared, there is not a single ideal value, just different optimum values for different scenarios!
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    [SOLVED] Ideal value of Form Factor for a rectifier

    The book I am reading from defines form factor as Vrms/Vdc
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    [SOLVED] Ideal value of Form Factor for a rectifier

    Hi, what is the ideal value for the form factor of a half and full wave rectifier? thanks
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    Implementing PI controller with non-ideal op amps

    Can you give an example of a new device for PI controller? I might try to implement it after I have successfully done it with the 741
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    Implementing PI controller with non-ideal op amps

    Hi all. I'm trying to implement a PI controller using op amps. I want to know what considerations I should keep in mind when designing the controller in hardware regarding the non-idealities of the 741 op amp.
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    Making a USB based Data logger using P18F4550.Confusion Regarding Software Resources.

    Hi all. I'm trying to make a data logger utilizing USB interface using a p18f4550. My requirement is that the data converted by the PIC's ADC would be available in MATLAB. I need help regarding the following - I'm confused as to which driver to use in the firmware. Should I go with the HID...
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    Multidriven Signals due to for loop in verilog

    Hi all, if A,B and C are 8 bit deep RAMS then why does this code produces a multidriven signal error for (i=0;i<16;i=i+1) begin for (j=0;j<8;j=j+1) begin A[i][j] = B[i][j] ^ C[i][j]; end end whereas this one produces no error for (i=0; i<16; i=i+1) begin A[i] = B[i] ^ C[i]; end
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    Declaring 2 RAMs together in Verilog?

    Is there a difference between the following two statements? reg [7:0] a,b [0:1023]; AND reg [7:0] a [0:1023]; reg [7:0] b [0:1023]; I'm just curious because declaring them together caused my code to go haywire, whilst declaring them separately solved everything!
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    Passing RAM as argument in tasks in Verilog

    HI all. Is it possible to pass a RAM as an argument in a verilog task. Also can a task return a value as a RAM? for example is the following code acceptable? task xyz(); input [7:0] reg_in [0:3]; output [7:0] reg_out [0:3]; endtask PS can a task return a value (like a C++ function)
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    Map : 116 - The design is empty. No processing will be done

    Thanks for the pointers r.b., I'll keep them in mind
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    Map : 116 - The design is empty. No processing will be done

    Can you please mention some, for future reference, so I may avoid these errors in future. Also I normally directly map my code after every few lines (like compiling a C++ code after every writing every few lines) just to check that I'm on the right track. Is this a good practice? This is my...
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    Map : 116 - The design is empty. No processing will be done

    Thanks for the quick reply How can a clock or reset stuck in an implementation module? Aren't these modules independent of initialization issues?
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    Map : 116 - The design is empty. No processing will be done

    Hi, i'm unable to figure out why i'm getting the following error. ERROR:Map:116 - The design is empty. No processing will be done. ERROR:Map:52 - Problem encountered processing RPMs. module AESEncryptor(InputPlainText, InputPassword, OutputCipherText, clk, rst_n ); input clk,rst_n...
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    Multiplying integer variables in verilog

    Its giving a syntax error whenever I try to do this. (HDLCompiler : 806, if that helps)
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    Multiplying integer variables in verilog

    Hi, Is it possible to multiply integer variable in a verilog for loop? example integer i,j = 0; for (i=0; i<10; i=i+1) j = 16 * (i+1);

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